The present invention generally relates to integrated circuits comprising both enhancement-mode and depletion-mode pseudomorphic high electron mobility transistor (PHEMT) devices and to methods of manufacturing the same.
Several types of field effect transistors (FETs) are available for use at microwave and millimeter wave frequencies. These high frequency FETs include metal semiconductor field effect transistors (MESFETs) and high electron mobility transistors (HEMTs), each of which is typically fabricated from Group III-V materials (xe2x80x9cIII-V semiconductorxe2x80x9d). A HEMT is distinguished from a MESFET in that charge is transferred from a charge donor layer to an undoped channel layer in a HEMT.
There are generally two types of HEMTs. One type is referred to simply as a HEMT, whereas the other type is referred to as a pseudomorphic HEMT or PHEMT. The difference between the HEMT and the PHEMT is that, in the PHEMT, one or more of the layers incorporated into the device has a lattice constant which differs significantly from the lattice constants of other materials of the device. As a result of this lattice mismatch, the crystal structure of the material forming the channel layer is strained. Although this lattice mismatch and the attendant strain makes growth of such devices more difficult than the growth of HEMTs, several performance advantages are obtained. For example, the charge density transferred into the channel layer is increased and high electron mobility and high electron saturated velocity are observed. As a result, the devices can develop higher power levels and can operate at higher frequencies with improved noise properties.
Devices are known, such as direct-coupled FET logic (DCFL) devices, which include both an enhancement-mode field effect transistor and a depletion-mode field effect transistor. These devices are characterized by low power consumption and are suited for constructing high-speed integrated circuits having a large integration density.
An enhancement-type transistor is a transistor that blocks the flow of current when no gate-source voltage is applied (also called a normally-off transistor). A depletion-type transistor is a transistor that allows current to flow when no gate-source voltage is applied (also called a normally-on transistor). Typically, the thickness of the active region upon which the gate contact is formed is different for each of these transistors, with this thickness being smaller for the enhancement-type transistor than it is for the depletion-type transistor.
The present invention is directed to novel PHEMT devices having both an enhancement-mode and a depletion-mode transistor (also referred to herein as xe2x80x9cenhancement/depletion PHEMT devicesxe2x80x9d) and to methods for making the same.
According to a first aspect of the invention, a depletion/enhancement PHEMT device structure is provided. The structure comprises: (a) a semiconductor substrate; (b) a buffer region comprising one or more semiconductor buffer layers over the substrate; (c) a III-V semiconductor channel layer over the buffer region; (d) an electron donor layer over the channel layer; (e) a GaAs or AlGaAs first schottky layer over the electron donor layer; (f) a first InGaP layer over the first schottky layer; (g) a GaAs or AlGaAs second schottky layer over the first InGaP layer; (h) a second InGaP layer over the second schottky layer; (i) a doped GaAs contact layer over the second InGaP layer; (j) an isolation structure extending from an upper surface of the contact layer at least to the buffer region, the isolation structure defining a first active region and a second active region; (k) an enhancement ohmic source contact and an enhancement ohmic drain contact disposed on the doped GaAs contact layer within the first active region; (l) an enhancement gate recess extending from an upper surface of the contact layer and through the first InGaP layer within the first active region; (m) an enhancement gate contact disposed over the first schottky layer within the enhancement gate recess; (n) a depletion ohmic source contact and a depletion ohmic drain contact disposed on the doped GaAs contact layer within the second active region; (o) a depletion gate recess extending from an upper surface of the contact layer and through the second InGaP layer within the second active region; and (p) a depletion gate contact disposed over the second schottky layer within the depletion gate recess.
Preferably, the semiconductor substrate is a GaAs substrate, the III-V semiconductor channel layer is an InGaAs channel layer, and the electron donor layer is a plane of silicon atoms.
The buffer region is preferably one comprising one or more III-V semiconductor layers, more preferably one comprising a GaAs buffer layer and a superlattice buffer comprising alternating layers of GaAs and AlGaAs.
The first schottky layer is preferably from 50 to 150 Angstroms in thickness, is preferably an AlxGa1-xAs layer, in which x ranges from 0.35 to 0.75, and is preferably undoped. The second schottky layer is preferably from 50 to 150 Angstroms in thickness, is preferably an AlxGa1-xAs layer in which x ranges from 0.15 to 0.25, and is preferably doped.
The first and second InGaP layers are preferably InzGa1-zP layers in which z ranges from 0.4 to 0.6, and they preferably range from 10 to 50 Angstroms in thickness.
The isolation structure is preferably an ion implanted structure.
In some preferred embodiments, the depletion/enhancement PHEMT device structure further comprises (a) a doped GaAs or AlGaAs transition layer between the second InGaP layer and the doped GaAs contact layer, in which the transition layer has a lower net doping concentration than the contact layer, (b) an undoped GaAs cap layer between the first schottky layer and the first InGaP layer, in which the cap layer ranges from 15 to 50 Angstroms in thickness, and/or (c) an AlGaAs spacer layer between the channel layer and the electron donor layer.
In some embodiments, the depletion gate recess is greater in aperture within its upper portions than it is within its lower portions, and the enhancement gate recess is greater in aperture within its upper portions than within its lower portions. More preferably, the depletion gate recess is greater in aperture within the doped GaAs contact layer than it is within the second InGaP layer, while the enhancement recess is greater in aperture within the doped GaAs contact layer and the second InGaP layer than it is within the second schottky layer and the first InGaP layer.
According to a second aspect of the invention, a method of forming a depletion/enhancement PHEMT device structure is provided. The method comprises:
(1) providing a multi-layer structure comprising: (a) a semiconductor substrate; (b) a buffer region over the substrate, the buffer region comprising one or more semiconductor buffer layers; (c) a III-V semiconductor channel layer over the buffer region; (d) an electron donor layer over the channel layer; (f) a GaAs or AlGaAs first schottky layer over the electron donor layer; (g) a first InGaP layer over the first schottky layer; (h) a GaAs or AlGaAs second schottky layer over the first InGaP layer; (i) a second InGaP layer over the second schottky layer; (j) a doped GaAs contact layer over the second InGaP layer; (k) ohmic contacts disposed on the doped GaAs contact layer; and (l) an isolation structure extending from an upper surface of the contact layer at least to the buffer region, with the isolation structure defining a first active region and a second active region;
(2) etching, within the first active region, an enhancement gate recess that extends from an upper surface of the contact layer down through the first InGaP layer;
(3) depositing an enhancement gate contact over the first schottky layer within the enhancement gate recess;
(4) etching, within the second active region, a depletion gate recess that extends from an upper surface of the contact layer down through the second InGaP layer; and
(5) depositing a depletion gate contact over the second schottky layer within the depletion gate recess.
The enhancement gate recess and the depletion gate recess are preferably etched using wet etching processes.
In a first preferred group of embodiments, the enhancement gate recess is etched by a process that includes the following steps: (a) etching a first active area recess from an upper surface of the contact layer to an upper surface of the second InGaP layer in a first enhancement recess etching step; (b) further etching the first active area recess through the second InGaP layer in a second enhancement recess etching step; (c) further etching the first active area recess to an upper surface of the first InGaP layer in a third enhancement recess etching step; and (d) further etching the first active area recess through the first InGaP layer in a fourth enhancement recess etching step to complete the enhancement gate recess. Also within this group of embodiments, the depletion gate recess is etched by a process that preferably includes the following steps: (a) etching a second active area recess from an upper surface of the contact layer to an upper surface of the second InGaP layer in a first depletion recess etching step; and (b) further etching the second active area recess through the second InGaP layer in a second depletion recess etching step to complete the depletion gate recess.
Within this first preferred group of embodiments, the first enhancement recess etching step, the third enhancement recess etching step and the first depletion recess etching step are preferably conducted using an aqueous etching solution comprising H2SO4 and H2O2, while the second enhancement recess etching step, the fourth enhancement recess etching step, and the second depletion etching step are preferably conducted using an aqueous etching solution comprising HCl.
Also within this first preferred group of embodiments, the first and second enhancement recess etching steps are preferably conducted such that an upper first active area recess having a first aperture is formed within the doped GaAs contact layer and within the second InGaP layer; and the third and fourth enhancement etching steps are preferably conducted such that a lower first active area recess having a second aperture narrower than the first aperture is formed within the second schottky layer and within the first InGaP layer.
Further within this first preferred group of embodiments, the third enhancement recess etching step is preferably performed concurrently with the first depletion recess etching step, the fourth enhancement recess etching step is preferably performed concurrently with the second depletion recess etching step, and the enhancement gate contact is preferably deposited concurrently with the depletion gate contact. The steps can also be performed independently.
In a second preferred group of embodiments, the multi-layer structure further comprises a doped GaAs or AlGaAs transition layer between the second InGaP layer and the doped GaAs contact layer, with the transition layer having a lower net doping concentration than the contact layer. Moreover, the enhancement gate recess is etched within this group of embodiments by a process comprising the following: (a) etching a first active area recess from an upper surface of the contact layer to an upper surface of the second InGaP layer in a first enhancement recess etching step; (b) further etching the first active area recess through the second InGaP layer in a second enhancement recess etching step; (c) further etching the first active area recess to an upper surface of the first InGaP layer in a third enhancement recess etching step; and (d) further etching the first active area recess through the first InGaP layer in a fourth enhancement recess etching step to complete the enhancement gate recess. Furthermore, the depletion gate recess is etched within this group of embodiments by a process comprising the following: (a) etching a second active area recess from an upper surface of the contact layer to an upper surface of the transition layer in a first depletion recess etching step; (b) further etching the second active area recess to an upper surface of the second InGaP layer in a second depletion recess etching step; and (c) further etching the second active area recess through the second InGaP layer in a third depletion recess etching step to complete the depletion gate recess.
Within this second preferred group of embodiments, (a) the first and second enhancement recess etching steps are preferably conducted such that an upper first active area recess having a first aperture is formed within the doped GaAs contact layer, within the transition layer, and within the second InGaP layer, (b) the third and fourth enhancement recess etching steps are preferably conducted such that a lower first active area recess having a second aperture narrower than the first aperture is formed within the second schottky layer and within the first InGaP layer, (c) the first depletion recess etching step is preferably conducted such that an upper second active area recess having a third aperture is formed within the doped GaAs contact layer, and (d) the second and third depletion recess etching steps are preferably conducted such that a lower second active area recess having a fourth aperture that is narrower than the third aperture is formed within the transition layer and within the second InGaP layer.
Also within this second preferred group of embodiments, the third enhancement recess etching step is preferably performed concurrently with the second depletion recess etching step, the fourth enhancement recess etching step is preferably performed concurrently with the third depletion recess etching step, and the enhancement gate contact is preferably deposited concurrently with the depletion gate contact.
Further within this second preferred group of embodiments, each of the first enhancement step, the third enhancement recess etching step and the second depletion recess etching step is preferably conducted using an aqueous etching solution comprising H2SO4 and H2O2, and each of the second enhancement recess etching step, the fourth enhancement recess etching step, and the third depletion step is preferably conducted using an aqueous etching solution comprising HCl.
One advantage of the present invention is that a PHEMT device containing both enhancement-mode and depletion-mode transistors can be achieved (1) with good control of the thickness of the active region adjacent the gate metal and (2) without using etch-stop materials that increase transistor source resistance.
Due to the etch stop materials used, another advantage of the present invention is that a PHEMT device containing both enhancement-mode and depletion-mode transistors can be achieved using wet etching techniques that: (1) involve conventional and easily controlled etching chemistry, (2) provide high selectivity, and (3) enable large volume batch mode etch operations, reducing considerably the capital equipment, labor content and cycle time associated with the device.
Another advantage of the present invention is that a PHEMT device containing both enhancement-mode and depletion-mode transistors can be achieved using relatively few process steps.
Yet another advantage of the present invention is that a PHEMT device containing both enhancement-mode and depletion-mode transistors can be achieved without resorting to techniques, such as reactive ion etching techniques, that prevent implementation of highly efficient batch-mode processing and can result in crystal damage and degrade transistor performance.
These and other embodiments and advantages of the present invention will be better understood by those of ordinary skill in the art upon review of the Detailed Description and claims to follow.